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BAC2 tech · Technology and Engineering II
Electrical and electronic systems · Combinational digital electronics

Logic functions and truth tables

Any logic function, however complicated it may seem, always boils down to the same pattern: products (AND) of variables, added together (OR). Here you will formalise that pattern with the canonical form, prove the Boolean laws that simplify it and discover that, at heart, a single universal gate is enough to build any circuit.

Before you start, make sure you know: Logic gates and digital circuits (4th ESO)
Before you start, make sure you know: Logic functions and circuit design (4th ESO)

The canonical form: sum of minterms

Truth table with the input combinations that give an output of one and their associated minterms to formulate the canonical sum a b c f minterm 0 0 11ā·b̄·c 1 0 11a·b̄·c 1 1 01a·b·c̄ f = ā·b̄·c + a·b̄·c + a·b·c̄
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Complete the truth table for the function $f = a \cdot b + \overline{c}$ for the eight combinations of inputs $a$, $b$, and $c$, and state in how many of them the output…

Complete the truth table for the function $f = a \cdot b + \overline{c}$ for the eight combinations of inputs $a$, $b$, and $c$, and state in how many of them the output is $1$.

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Explain what the canonical form of a logic function is (sum of products with all variables in each term) and why any truth table has a unique canonical form, even though…

Explain what the canonical form of a logic function is (sum of products with all variables in each term) and why any truth table has a unique canonical form, even though it may admit many equivalent simplified expressions.

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From this partial truth table the outputs are known: $f(0,0,0) = 0$, $f(0,0,1) = 1$, $f(0,1,0) = 0$, $f(0,1,1) = 1$, $f(1,0,0) = 0$, $f(1,0,1) = 0$, $f(1,1,0) = 1$,…

From this partial truth table the outputs are known: $f(0,0,0) = 0$, $f(0,0,1) = 1$, $f(0,1,0) = 0$, $f(0,1,1) = 1$, $f(1,0,0) = 0$, $f(1,0,1) = 0$, $f(1,1,0) = 1$, $f(1,1,1) = 1$. Obtain the canonical function as a sum of products (minterms) for the combinations that give $1$ and simplify it by applying properties of Boolean algebra.

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De Morgan's laws

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Prove De Morgan's laws using truth tables: $\overline{a \cdot b} = \overline{a} + \overline{b}$ and $\overline{a + b} = \overline{a} \cdot \overline{b}$. Explain in your…

Prove De Morgan's laws using truth tables: $\overline{a \cdot b} = \overline{a} + \overline{b}$ and $\overline{a + b} = \overline{a} \cdot \overline{b}$. Explain in your own words what these laws allow you to do when designing circuits.

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Simplify $f = \overline{\overline{a} + b}$ by applying De Morgan's laws and double negation, step by step, indicating each law used. Then draw the original circuit (NOT,…

Simplify $f = \overline{\overline{a} + b}$ by applying De Morgan's laws and double negation, step by step, indicating each law used. Then draw the original circuit (NOT, OR, NOT) and the simplified one, and count the gates saved.

You can do it on paper and send a photo with your answer.

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In the control of a smart pedestrian traffic light, you design the circuit for the pedestrian green light ($V = 1$) based on three signals: pedestrian pushbutton ($P$),…

In the control of a smart pedestrian traffic light, you design the circuit for the pedestrian green light ($V = 1$) based on three signals: pedestrian pushbutton ($P$), approaching emergency vehicle sensor ($A$), and rush hour timer ($T$). The safety specifications are:

  1. If an emergency vehicle is detected ($A = 1$), the pedestrian light must remain red ($V = 0$) under any circumstance.

  2. In the absence of emergencies, pedestrian right-of-way is granted if the pedestrian requests it ($P = 1$) or if the timer indicates an automatic cycle ($T = 1$).

  3. For intrinsic safety against wire breakage, the sensors are wired with active-low logic: the pressed pushbutton delivers $P = 0$ (at rest $P = 1$) and the presence of an ambulance delivers $A = 0$ (at rest $A = 1$). The timer maintains active-high logic ($T = 1$).

  1. a) Build the truth table for output $V$ as a function of the actual measured logic signals ($A, P, T$).
  2. b) Obtain the simplified logic function in sum of products using a Karnaugh map.
  3. c) Justify what would happen to the safety of the intersection if the emergency sensor wire $A$ is accidentally cut (remaining at logic level $0$ due to a pull-down resistor) versus if it remains at high level ($1$). Which of the two options represents a fail-safe design?
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Algebraic simplification: common factor and absorption

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Verify with reasoning (without tables) these properties of Boolean algebra: $a + 1 = 1$, $a \cdot 0 = 0$, $a + a = a$, $a \cdot \overline{a} = 0$. What does each one…

Verify with reasoning (without tables) these properties of Boolean algebra: $a + 1 = 1$, $a \cdot 0 = 0$, $a + a = a$, $a \cdot \overline{a} = 0$. What does each one physically mean if $a$ is a switch?

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Prove the absorption law $a + a \cdot b = a$ in two ways: algebraically (by factoring out the common term) and with the truth table. Explain what practical use this law…

Prove the absorption law $a + a \cdot b = a$ in two ways: algebraically (by factoring out the common term) and with the truth table. Explain what practical use this law has when simplifying digital circuits.

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The emergency stop circuit of an industrial packaging machine responds to three sensors $A, B, C$ according to the expression: $$P = \overline{A} \cdot B \cdot C + A…

The emergency stop circuit of an industrial packaging machine responds to three sensors $A, B, C$ according to the expression:

$$P = \overline{A} \cdot B \cdot C + A \cdot \overline{B} \cdot C + A \cdot B \cdot C + A \cdot B \cdot \overline{C}$$

It is currently assembled using inverters, 3-input AND gates, and a 4-input OR gate.

  1. a) Simplify the function $P$ using a Karnaugh map to obtain the minimal sum-of-products expression. How many total gates and inputs do you save compared to the original assembly?
  2. b) An operator states: "We can replace the entire circuit with a single three-input XOR gate, $P = A \oplus B \oplus C$, because the truth table matches for most combinations." Prove using the truth table whether this statement is true or false, indicating for which input combinations the machine would behave incorrectly.
  3. c) Analyze the simplified function on the Karnaugh map: if the inputs transition from $ABC = 110$ to $ABC = 111$, predict with justification whether there is a risk of a spurious transient pulse (glitch or static 1-hazard) appearing at the output due to the switching delays of the gates, and justify how this hazard would be resolved.
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The NAND gate is universal

Universal NAND gate: a NAND with its inputs joined acts as a NOT, two NANDs in series give AND, and with three NANDs OR is obtained by De Morgan NOT with NAND a NAND = ā AND with NAND+NAND a b NAND NAND = a·b OR with NAND (De Morgan): a+b = ¯(ā·b̄) Each input is negated with a NAND-NOT and they are combined with a third NAND. NAND NAND NAND a+b a b
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Write the truth table of the two-input NOR gate ($A$ and $B$) and explain how it is built from an OR gate and a NOT gate. State in one sentence when its output is $1$.

Write the truth table of the two-input NOR gate ($A$ and $B$) and explain how it is built from an OR gate and a NOT gate. State in one sentence when its output is $1$.

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In a production line, you must implement the stop circuit for an actuator whose simplified Boolean equation is $S = \overline{A \cdot B} + C$. In the warehouse, you only…

In a production line, you must implement the stop circuit for an actuator whose simplified Boolean equation is $S = \overline{A \cdot B} + C$. In the warehouse, you only have 74HC00 integrated circuits available (each IC contains 4 independent two-input NAND gates).

A technician directly replaces each operator with its standard equivalent and claims that they will need 2 complete ICs (5 NAND gates in total).

  1. a) Formally prove using De Morgan's laws and Boolean algebra that it is possible to implement function $S$ using only 4 two-input NAND gates, indicating which signals you must connect to each input.
  2. b) Draw the circuit diagram of the optimized circuit and reason how many 74HC00 integrated circuits are actually needed.
  3. c) In the CMOS technology of the 74HC00 IC, predict what technical problem would occur if you leave the inputs of the unused gates floating in an industrial environment with electromagnetic noise, and justify how they should be connected to avoid excessive power consumption or chip breakdown.
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An emergency cooling system must activate a turbine ($T = 1$) based on the state of three variables: critical pressure ($P$), high temperature ($E$), and forced…

An emergency cooling system must activate a turbine ($T = 1$) based on the state of three variables: critical pressure ($P$), high temperature ($E$), and forced ventilation failure ($V$). Safety requirements dictate that the turbine must activate for the minterms: $T(P, E, V) = \sum m(1, 2, 5, 6, 7)$.

To save board space, it is decided to implement the entire logic using a single commercial multiplexer with 4 data inputs ($D_0, D_1, D_2, D_3$) and 2 select inputs ($S_1, S_0$), without adding any external logic gates.

  1. a) Justify the theoretical basis of using a multiplexer as a universal logic function generator.
  2. b) If you connect variables $P$ and $E$ to the select inputs ($S_1 = P, S_0 = E$), determine with justification what constant value ($0, 1$) or signal ($V, \overline{V}$) must be connected to each data input $D_0, D_1, D_2$, and $D_3$.
  3. c) If due to wiring constraints the select inputs are swapped such that $S_1 = V$ and $S_0 = E$, find the new functions that must be fed into $D_0, D_1, D_2, D_3$ in terms of the remaining variable $P$.
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Summary

See all the exercises in this section