Flip-flops and sequential circuits

Explain the fundamental difference between a combinational circuit and a sequential one, and explain why a counter for people entering a venue cannot be built using only combinational gates.

Describe the operation of an SR flip-flop: what inputs $R$ and $S$ do, what the "memory" state means, and why the combination $R = 1$, $S = 1$ is forbidden in its basic version.

The mechanical contacts of a push-button "bounce" for a few milliseconds and produce several false pulses in a counter. Explain the phenomenon of contact bounce, why an SR flip-flop connected to a switch eliminates it (the first contact sets the state and subsequent bounces do not change it), and what other solutions exist (RC filter, software debouncing).

The figure shows the timing diagram of a rising-edge-triggered D flip-flop: the clock signal and input $D$ are represented, and output $Q$ is covered. Assuming that the initial state of the output is $Q = 0$, draw output $Q$ during the four cycles yourself and explain the rule you have applied at each edge.

You can do it on paper and send a photo with your answer.

Explain what a timing diagram is in digital electronics: what the horizontal axis represents, what the high and low levels of each signal represent, and why it is the fundamental tool for analysing sequential circuits.

Distinguish between a level-triggered latch (transparent while the enable signal is high) and an edge-triggered flip-flop (only copies at the instant of the edge). Why do synchronous systems prefer edge triggering?

Describe the T (toggle) flip-flop: what its output does on each active pulse of the input and why it is equivalent to "dividing the frequency by two". What is its truth table?

Explain what problem of the SR flip-flop is solved by clock-synchronised flip-flops (D and JK): what a rising edge is, what the D flip-flop copies on each edge, and how the JK flip-flop avoids the forbidden state with its "toggle" mode.

The figure shows the timing diagram of a negative-edge-triggered JK flip-flop, with $J = 1$ permanently and a variable $K$. Complete the output $Q$ cycle by cycle (initially $Q = 0$) applying the JK truth table and explain which operating mode (hold/memory, set to 1, reset to 0, toggle/inversion) is used at each edge.

Three cascaded D flip-flops, each triggered by output $\overline{Q}$ of the previous one, form an asynchronous counter. Explain why each stage divides the frequency by two and write the sequence of outputs $Q_2 Q_1 Q_0$ during the first eight clock pulses. What maximum number does it count to, and what happens on the next pulse?

Describe a four-bit shift register with serial input: what happens to the data present at the input on each clock pulse and where it travels. Write the content of the register after entering the sequence $1$, $0$, $1$, $1$ (one bit per pulse), assuming it starts empty.

To control access to an area with capacity limited to 3 vehicles, you need to design a two-bit synchronous counter ($Q_1 Q_0$) that records the number of occupied spaces. The system must start at $0$ ($00_2$), increment with each vehicle passing pulse ($01_2$, $10_2$, $11_2$) and, once the maximum capacity of $3$ ($11_2$) is reached, it must remain in that state ignoring new input pulses so as not to overflow, simultaneously activating a blocking indicator light $B = 1$.

1. a) Build the state transition table and derive the simplified excitation functions to implement it with rising-edge-triggered JK flip-flops.
2. b) Obtain the logic equation for the blocking signal $B$ and draw the schematic of the complete logic circuit.
3. c) Draw the timing diagram of the outputs $Q_1$, $Q_0$, and $B$ for a sequence of five consecutive clock pulses starting from a count of zero.