Exercises: Flip-flops and sequential circuits

Explain the fundamental difference between a combinational circuit and a sequential one, and explain why a counter for people entering a venue cannot be built using only combinational gates.

Describe the operation of an SR flip-flop: what inputs $R$ and $S$ do, what the "memory" state means, and why the combination $R = 1$, $S = 1$ is forbidden in its basic version.

The figure shows the timing diagram of a rising-edge-triggered D flip-flop: the clock signal and input $D$ are represented, and output $Q$ is covered. Assuming that the initial state of the output is $Q = 0$, draw output $Q$ during the four cycles yourself and explain the rule you have applied at each edge.

You can do it on paper and send a photo with your answer.

Explain what a timing diagram is in digital electronics: what the horizontal axis represents, what the high and low levels of each signal represent, and why it is the fundamental tool for analysing sequential circuits.

Describe the T (toggle) flip-flop: what its output does on each active pulse of the input and why it is equivalent to "dividing the frequency by two". What is its truth table?

Distinguish between a level-triggered latch (transparent while the enable signal is high) and an edge-triggered flip-flop (only copies at the instant of the edge). Why do synchronous systems prefer edge triggering?

Explain the operation of a D latch: what happens to input $D$ while enable is active and what the output stores when it is deactivated. Why is it said to be "transparent"?

Give four real-world applications of digital counters (parking spaces, frequency counter, digital wall clock, engine revolutions) and explain for each one which signal is counted and how the count is used.

Explain what problem of the SR flip-flop is solved by clock-synchronised flip-flops (D and JK): what a rising edge is, what the D flip-flop copies on each edge, and how the JK flip-flop avoids the forbidden state with its "toggle" mode.

Three cascaded D flip-flops, each triggered by output $\overline{Q}$ of the previous one, form an asynchronous counter. Explain why each stage divides the frequency by two and write the sequence of outputs $Q_2 Q_1 Q_0$ during the first eight clock pulses. What maximum number does it count to, and what happens on the next pulse?

Describe a four-bit shift register with serial input: what happens to the data present at the input on each clock pulse and where it travels. Write the content of the register after entering the sequence $1$, $0$, $1$, $1$ (one bit per pulse), assuming it starts empty.

The figure shows the timing diagram of a negative-edge-triggered JK flip-flop, with $J = 1$ permanently and a variable $K$. Complete the output $Q$ cycle by cycle (initially $Q = 0$) applying the JK truth table and explain which operating mode (hold/memory, set to 1, reset to 0, toggle/inversion) is used at each edge.

You need a $1\ \text{Hz}$ signal from a $4\ \text{Hz}$ oscillator. Explain how to obtain it with two cascaded T flip-flops (each divides by two) and draw the timing diagram of the three signals (input, intermediate output, and final output) over two seconds.

You can do it on paper and send a photo with your answer.

An $8$-bit shift register receives serial data and, after eight pulses, delivers it in parallel. Explain what conversion it performs (serial-to-parallel) and a real application: lighting eight LEDs using only two lines from a microcontroller (data and clock).

A synchronous counter must count from $0$ to $5$ and reset (modulo 6). Explain how combination $6$ ($110$) is detected using a gate and how the asynchronous reset is forced, and state the limitation of this method (state $6$ exists for a very brief instant).

The mechanical contacts of a push-button "bounce" for a few milliseconds and produce several false pulses in a counter. Explain the phenomenon of contact bounce, why an SR flip-flop connected to a switch eliminates it (the first contact sets the state and subsequent bounces do not change it), and what other solutions exist (RC filter, software debouncing).

To control access to an area with capacity limited to 3 vehicles, you need to design a two-bit synchronous counter ($Q_1 Q_0$) that records the number of occupied spaces. The system must start at $0$ ($00_2$), increment with each vehicle passing pulse ($01_2$, $10_2$, $11_2$) and, once the maximum capacity of $3$ ($11_2$) is reached, it must remain in that state ignoring new input pulses so as not to overflow, simultaneously activating a blocking indicator light $B = 1$.

1. a) Build the state transition table and derive the simplified excitation functions to implement it with rising-edge-triggered JK flip-flops.
2. b) Obtain the logic equation for the blocking signal $B$ and draw the schematic of the complete logic circuit.
3. c) Draw the timing diagram of the outputs $Q_1$, $Q_0$, and $B$ for a sequence of five consecutive clock pulses starting from a count of zero.

An emergency stop system monitors a 4-bit asynchronous up-counter ($Q_3 Q_2 Q_1 Q_0$). Each flip-flop has a propagation delay time of $t_{pd} = 12\ \text{ns}$. An AND gate connected to the outputs must trigger an alarm only when the count reaches the number $8$ ($1000_2$), with a gate response time of $4\ \text{ns}$.

1. a) During the transition from state $7$ ($0111_2$) to state $8$ ($1000_2$), deduce in detail all the intermediate transient states assumed by the outputs until their stabilization, indicating the exact duration of each.
2. b) Justify whether a false trigger (spurious pulse or glitch) of the alarm will occur during the transition from $7$ to $8$, or if the alarm were connected to detect state $0$ ($0000_2$).
3. c) Calculate the maximum allowable clock frequency for the 4-bit counter to operate reliably without overlapping transitions, and explain how a synchronous counter eliminates this risk.

It is desired to implement occupancy control for a 15-space parking lot using a 4-bit reversible (up/down) binary synchronous counter ($Q_3 Q_2 Q_1 Q_0$). Two mechanical sensors generate a signal upon detecting an entering vehicle ($E$) or an exiting one ($S$).

1. a) Mechanical pushbuttons produce switch bouncing that distorts the count. Design the debouncing circuit for one of the inputs using an RS flip-flop built with NAND logic gates and a changeover switch, justifying its operation.
2. b) If a vehicle enters at the exact same instant another leaves, both signals coincide. Design a preliminary logic block or reason a synchronization strategy that prevents the simultaneous entry of two pulses to the counter and determines which of the two events must be safely processed.
3. c) Determine the control logic functions so that the counter does not decrement below $0000_2$ (empty parking lot) nor increment above $1111_2$ (full parking lot), activating a warning light in the latter case.

An urban intersection is regulated by a traffic light whose lights (Green $V$, Amber $A$, and Red $R$) follow a strict cycle of four time intervals: Green for $30\ \text{s}$, Amber for $6\ \text{s}$, Red for $24\ \text{s}$, and Red with Amber for $6\ \text{s}$. A clock signal with a period of $6\ \text{s}$ is available.

1. a) Determine the total number of elementary states that make up a full cycle and the minimum number of flip-flops required to implement the synchronous control counter.
2. b) Assign binary states and obtain the simplified logic equations for turning on each of the three lamps ($R$, $A$, and $V$) as a function of the counter outputs.
3. c) Design the counter using edge-triggered JK flip-flops, deriving the excitation functions and showing the feedback wiring to restart the cycle at the exact instant.

An $8$-bit asynchronous counter is driven at $10\ \text{MHz}$. Each flip-flop takes $10\ \text{ns}$ to propagate the change. a) Calculate the total delay until the last bit is valid. b) Compare it with the input period and explain up to what frequency the reading of the complete counter can be trusted. c) How does a synchronous counter solve the problem and at what price (more logic)?

Design a synchronous sequential sequence detector system on a serial binary data line $X$ synchronized with a common clock. The output $Z$ must go high ($Z = 1$) each time three consecutive ones ($111$) are detected, allowing overlap (for example, the input sequence $...011110...$ must generate the sequence $...000110...$ at $Z$).

1. a) Model the system using a finite state machine (state diagram) following the Moore model, indicating the meaning of each state.
2. b) Assign binary state codes and obtain the transition table and simplified excitation functions to implement the circuit using D flip-flops.
3. c) Draw the complete logic diagram of the resulting circuit and reason what would happen at output $Z$ if a spurious noise pulse with a duration shorter than half a clock period is introduced into $X$.

A digital computing circuit must perform the arithmetic operation $Y = 5 \cdot X + 2$ with minimum latency and without a dedicated arithmetic processor, starting from a 4-bit positive integer input data $X$ ($X = X_3 X_2 X_1 X_0$) stored in a register.

1. a) Demonstrate how multiplication by $5$ can be decomposed using exclusively left-shift and parallel addition operations. Specify how many shifts are required and what weight each shifted bit acquires.
2. b) Design the basic cell of an internal stage $Q_i$ of a universal shift register using a D flip-flop and a $4:1$ multiplexer, detailing the truth table of the selection lines $S_1 S_0$ for the following modes: hold data ($00$), shift right ($01$), shift left ($10$), and parallel load of $X_i$ ($11$).
3. c) If the input data is $X = 0011_2$ ($3_{10}$), predict the binary value of the register after applying the sequence: parallel load $\rightarrow$ shift left $\rightarrow$ shift left. Justify how many bits the final adder must have to avoid any overflow with 4-bit inputs.

You want to design the timing circuit of a digital stopwatch for a sports event that counts from $00$ to $59\ \text{s}$ with a resolution of $1\ \text{s}$. The starting point is a commercial quartz crystal oscillator of $32.768\ \text{kHz}$ ($32\,768\ \text{Hz} = 2^{15}\ \text{Hz}$).

1. a) Justify the exact number of T flip-flops required in a divider chain to reduce the oscillator frequency to a clock signal of exactly $1\ \text{Hz}$, indicating whether any additional feedback gates are needed.
2. b) Design the complete connection between two integrated BCD counters (seconds units, modulo 10, and seconds tens, modulo 6): specify which outputs are taken to generate the clock for the second counter and what combinational logic must act on the clear input (reset) so that the tens modulus is exactly 6.
3. c) Design the start/stop control circuit (Start/Stop) using a single normally open pushbutton and a flip-flop, reasoning at which point in the chain said signal must be inserted to freeze the count without resetting the accumulated value.

Topic Challenge. Design a sequential control system to optimize domestic battery charging based on grid electricity demand.

1. Go to the Red Eléctrica de España (REE) website and extract the real-time peninsular demand data from the last $24\text{ h}$. Define three consumption levels: off-peak ($<23,5\text{ GW}$), mid-peak ($23,5-31,0\text{ GW}$), and on-peak ($>31,0\text{ GW}$).

2. Design a synchronous sequential circuit (Moore machine) with three states ($S_0, S_1, S_2$) encoded using two flip-flops (D or JK type). An external input $X$ will indicate whether demand is increasing ($X=1$) or decreasing ($X=0$). Obtain the transition table, the flip-flop excitation table, and simplify the input functions using Karnaugh maps.

3. Build and simulate the circuit in Tinkercad Circuits (using integrated circuits such as the 74HC74), verifying state changes with a manual or generated clock signal ($CLK$).

4. Write a brief report with the state diagram, the obtained logic functions, a screenshot of the simulated circuit, and the timing diagram verifying its correct operation.

Evaluation criteria:

• Rigor in obtaining and categorizing the real data from REE.

• Analytical correctness in sequential synthesis (flip-flop tables, Karnaugh maps, and simplified equations).

• Correct operation and timing diagram consistency in the Tinkercad simulation.