Exercises: Integrated combinational blocks

Explain what a medium-scale integration (MSI) integrated circuit is compared to assembling the same using individual logic gates: advantages in terms of size, reliability and cost. Name three typical MSI blocks and an application of each.

Explain what a $n$-input to $2^n$-output decoder does: what binary combination it receives and what exactly happens at its outputs (only one is activated, corresponding to the input code). Give the example of a $2$-to-$4$ decoder with its complete truth table.

Explain what a multiplexer does: how many data inputs and how many select inputs a $4$-channel multiplexer has, and what appears at its single output. Compare it to the source selector of an audio amplifier (CD, radio, auxiliary).

Explain what a demultiplexer does and how it differs from a multiplexer (a data input routed to one of several outputs, chosen by the select inputs). Provide an analogy with a railway switch that routes a train carriage to one of four tracks.

Explain what a half adder adds (two bits) and what two outputs it produces (sum and carry). Explain why it is called a "half" adder: what input is missing for it to be cascaded in adding multi-bit numbers.

Explain what additional input a full adder has compared to a half adder (the carry-in, $C_{in}$) and why it is essential when adding multi-bit numbers: describe the role played by the carry that "travels" from one column to the next, just like in manual decimal addition.

Explain what a BCD to 7-segment decoder does ($7$ segments): what code it receives at its four inputs, what it activates at its seven outputs, and for which display it is used. Explain what happens with the input combinations from $10$ to $15$, which are not valid BCD digits.

Explain what a digital comparator does: what two data inputs it receives and what three outputs it can provide ($A > B$, $A = B$, $A < B$). Give two applications: a digital thermostat that compares the measured temperature with the setpoint, and a system that detects whether a counter has reached its maximum value.

A $3$-to-$8$ decoder receives the code $101$ at its inputs (with the most significant bit on the left). a) State which output is activated, numbering the outputs from $0$ to $7$. b) Write the complete truth table of the decoder. c) Describe an application: selecting one of eight memory devices sharing the same data bus.

The figure shows a $4$-channel multiplexer with the values of its data inputs and its select inputs. a) Write its selection table (which channel passes to the output for each value of $S_1 S_0$). b) Determine the value of the output marked with the question mark. c) Explain what would need to be changed so that the value of channel $D_1$ is output.

The figure shows the circuit of a half adder with its truth table to be completed. a) Fill in the sum ($S$) and carry ($C$) columns in your notebook for the four input combinations. b) Identify which gate produces each output and write the two logic functions. c) Check with the table that the set $\{S, C\}$ represents the arithmetic sum of $a$ and $b$ in binary.

The figure shows a $4$-bit adder consisting of four cascaded full adders, with the two addends $A = 0101$ and $B = 0011$ applied. a) Solve the addition step by step, indicating the carry coming out of each stage. b) Write the result and its final carry, and check in decimal that it is correct. c) Explain what would happen if the result required $5$ bits and there were only outputs for $4$ (overflow).

State how many select lines a $8$-channel multiplexer needs and how many a $16$-channel one needs, and write the general relationship between channels and select lines. Apply this to choosing a multiplexer to read data from $6$ sensors using a single wire: what commercial size would you choose and which channels would remain free?

A BCD to 7-segment decoder ($7$ segments) receives the code $0101$. a) State which digit that BCD code represents. b) Write which segments of the display must light up to show it (name them using the standard convention: $a$ the top one, $b$ and $c$ the right-hand ones, $d$ the bottom one, $e$ and $f$ the left-hand ones, and $g$ the middle one). c) Explain what the circuit does if it receives the code $1100$.

A $1$-to-$4$ demultiplexer has its data input at $1$ and its select inputs at $S_1 S_0 = 01$. a) State which output will present $1$ and what value the others will have. b) Write its function table. c) Describe an application: distributing the clock signal of a system to one of four modules selected at any given time.

Set up a $1$-bit comparator: write its truth table with inputs $A$ and $B$ and outputs $A > B$, $A = B$ and $A < B$, and deduce the logic function for each output. Comment on which gates you need to implement it and how the output $A = B$ relates to the XNOR gate.

An industrial safety module must activate a stop signal ($P=1$) based on the state of three binary sensors ($a, b, c$), satisfying the function $P(a,b,c) = \sum m(1, 3, 6, 7)$. To implement it, a commercial 8-to-1 channel multiplexer is available with select inputs $S_2, S_1, S_0$ and data inputs $I_0$ to $I_7$.

1. a) Design the multiplexer wiring indicating which logic level ('0' or '1') each data input must be connected to if the select signals are assigned as $S_2=a$, $S_1=b$, and $S_0=c$.
2. b) During board assembly, a technician mistakenly swaps the select lines by connecting $S_2=c$, $S_1=b$, and $S_0=a$, while keeping the data inputs calculated in the previous section. Derive the truth table of the function that the circuit actually executes and indicate for which sensor combinations a false trigger (unwanted stop) or a missed trigger (the system fails to stop when it should) will occur.
3. c) Justify why using a multiplexer is more advantageous than a design with minimal logic gates during the prototyping stage if the system trigger conditions could change in subsequent revisions.

To optimize board space, it is decided to replace the 8-channel multiplexer from the previous exercise with a 4-channel one ($S_1, S_0$ and data $I_0, I_1, I_2, I_3$) to generate the same function $f(a,b,c) = \sum m(1, 3, 6, 7)$.

1. a) Implement the function using $b$ and $c$ as select inputs ($S_1=b, S_0=c$). Obtain the implementation table and determine which signal ($0$, $1$, $a$, or $\overline{a}$) must be applied to each data input $I_k$.
2. b) A teammate claims that, if $S_1=a$ and $S_0=b$ are chosen as select inputs, it is possible to implement the circuit without needing any external inverter for the remaining variable. Formally justify whether this statement is true or false by deriving the signal required at each data input under this alternative configuration.
3. c) Compare both alternatives against the 8-channel multiplexer solution in terms of the number of integrated circuit pins and required external auxiliary components.

In the arithmetic logic unit (ALU) of a processor, 1-bit full adder modules are used (inputs $A, B, C_{in}$; outputs $S, C_{out}$).

1. a) Formally prove, based on the properties of binary addition, why the sum output $S$ is equivalent to the odd parity function of the inputs ($A \oplus B \oplus C_{in}$) and why the carry-out $C_{out}$ matches the majority function (it equals '1' if at least two of the three inputs are '1').
2. b) Design the implementation of both outputs ($S$ and $C_{out}$) using exclusively two 4-to-1 multiplexers whose common select inputs are $A$ and $B$, determining what must be connected to each data input of both multiplexers in terms of $C_{in}$, '0', or '1'.
3. c) If in the standard carry implementation, $C_{out} = A\cdot B + C_{in}\cdot(A \oplus B)$, the XOR gate suffers a failure that leaves its output permanently fixed at a low level ('stuck-at-0'), predict with justification for which input combinations $(A, B, C_{in})$ the carry output will provide an incorrect value.

For an industrial weighing system, two 4-bit binary words, $A = a_3 a_2 a_1 a_0$ and $B = b_3 b_2 b_1 b_0$, need to be compared using cascaded 2-bit integrated comparator blocks.

1. a) Derive the simplified logic functions for the equality ($A=B$) and greater-than ($A>B$) outputs for a 2-bit comparator block ($a_1 a_0$ versus $b_1 b_0$), expressed using XNOR gates for bitwise equality.
2. b) Draw the block interconnection diagram of two 2-bit comparators to form the 4-bit comparator. Justify which fixed logic levels must be connected to the cascade inputs ($I_{A>B}$, $I_{A
3. c) If during operation the trace connecting the $A=B$ output of the most significant stage to the corresponding input of the next stage is broken, leaving that internal input floating at '0', predict with reasoning the result of the overall comparison for the following pairs of values:

1) $A = 1101_2$ and $B = 1100_2$

2) $A = 1011_2$ and $B = 0111_2$

In which of the two cases will the system indicate an incorrect diagnosis, and why?

An arithmetic logic unit must perform 16-bit additions in a single clock cycle of $20\ \text{ns}$ (clock frequency of $50\ \text{MHz}$). 1-bit full adder cells are available with the following timing characteristics:

• Propagation delay from any input to the carry output: $t_{C} = 1,8\ \text{ns}$.

• Propagation delay from any input to the sum output: $t_{S} = 2,4\ \text{ns}$.

1. a) If 16 full adders are connected in cascade (ripple-carry adder), calculate the worst-case delay. Describe what condition on the input operands causes this critical delay and justify whether this adder meets the clock cycle time limit.
2. b) As an alternative, a carry-lookahead adder (CLA) is proposed. Define the carry generation ($G_i$) and carry propagation ($P_i$) variables for stage $i$, and derive the Boolean expression for carry $C_4$ as a function solely of $C_0$ and the $P$ and $G$ terms of stages 0 to 3.
3. c) Based on the equation obtained for $C_4$, explain why manufacturers do not design 16- or 32-bit CLA adders with a single direct multilevel block, explaining what physical limitations of fan-in (number of inputs per gate) and capacitive loading prevent it.

A microprocessor needs to address 16 independent peripherals (outputs $Y_0$ to $Y_{15}$, active low) using a 4-bit address bus ($A_3, A_2, A_1, A_0$). 3-to-8 line decoder integrated circuits are available, each featuring three enable pins: two active low ($\overline{E_1}$ and $\overline{E_2}$) and one active high ($E_3$).

1. a) Design the connection diagram of two 3-to-8 decoders to build the full 4-to-16 decoder. Show how the circuit can be implemented without adding any external inverter gate for the most significant bit ($A_3$), taking advantage of the polarity of the different enable inputs.
2. b) Detail the assignment of each bus line ($A_3, A_2, A_1, A_0$) to the selection and enable pins of each integrated circuit, indicating which IC generates the outputs $Y_0\dots Y_7$ and which generates the outputs $Y_8\dots Y_{15}$.
3. c) If, due to a soldering defect, the enable pin $E_3$ of the lower-order IC becomes disconnected (behaving as a low level '0'), predict with justification what will happen when trying to select peripheral 3 ($A = 0011_2$) and what will happen when selecting peripheral 11 ($A = 1011_2$).

The 74xx138 integrated circuit is marketed as a "3-to-8 line Decoder / Demultiplexer". It features three selection inputs ($S_2, S_1, S_0$), one data/enable input ($E$), and eight active-low outputs ($Y_0$ to $Y_7$, where each is activated at '0').

1. a) Demonstrate its operation as a demultiplexer: if you want to route a serial binary data stream $D$ to one of the 8 output lines according to the selection code, indicate which pin signal $D$ is connected to and write the Boolean expression for the generic output $Y_k$ as a function of $D$ and the selection minterms.
2. b) Explain how input $E$ must be set so that the device operates as a pure binary memory address decoder with active-low outputs.
3. c) An engineer claims that with a single 74xx138 integrated circuit and a single external 4-input NAND gate, any 3-variable combinational logic function containing up to 4 minterms can be implemented. Prove whether the statement is true or false by implementing the function $f(A,B,C) = \sum m(1, 2, 4, 7)$ as an example and justifying the design using De Morgan's laws.

A display system for the occupancy of a car park (from 0 to 99 vehicles) is planned, controlled by a two-digit BCD up/down counter that receives pulses from entry and exit barrier sensors.

1. a) Draw the detailed block diagram of the system (BCD counter, BCD to 7-segment decoders, and displays). Justify the choice of a BCD counter architecture over one based on a 7-bit natural binary counter ($2^7 = 128$), comparing the complexity of the decoder block required in each case.
2. b) If common-cathode displays are used, but by mistake decoders designed for common-anode displays are installed, predict exactly which segment pattern will illuminate on the display when the counter indicates the digit '0'. Prove it by indicating the segments that should light up and those that will actually light up.
3. c) To avoid unwanted readings, when the occupancy is less than 10 people, the tens display must turn off completely (leading zero blanking). Design the simplified combinational circuit that, taking the 4 BCD bits of the tens digit ($D_3, D_2, D_1, D_0$), activates the blanking pin (Blanking Input, $\overline{BI}$, active low) of the tens decoder.
4. d) Design using logic gates a "Full" warning light signal ($LL=1$) that is activated only when the counter reaches exactly the value 99, optimizing the function from the tens and units bits.

Topic Challenge. Design a home automation energy manager to optimize domestic electricity consumption based on real-time energy costs.

1. Data collection and truth table: Check today's hourly PVPC electricity rates on the Red Eléctrica de España website (REE or pvpc.es). Define three boolean input variables ($A, B, C$) based on real thresholds (for example: $A=1$ if the price exceeds $0,15$ €/kWh, $B=1$ if it is peak hours, and $C=1$ if there is simulated solar surplus). Draw up the truth table for controlling two loads: electric water heater ($S_1$) and HVAC ($S_2$).

2. Simplification: Obtain the canonical function of $S_1$ and simplify it using Karnaugh maps to minimize the cost in logic gates.

3. Integrated blocks and simulation: Implement $S_2$ using a 4-input or 8-input multiplexer as an integrated combinational block. Model and simulate the complete circuit in Tinkercad Circuits or Simulator.io.

4. Technical proposal: Prepare a brief report (2 pages) with the REE data, the table, the Karnaugh maps, the circuit schematic, and a technical justification on when it is advantageous to use multiplexers over discrete logic gates.

Evaluation criteria:

• Rigor in data collection from REE and logical consistency of the truth table.

• Mathematical correctness in the Karnaugh simplification of $S_1$.

• Proper functional implementation of $S_2$ with a multiplexer in the simulator.

• Clarity and technical justification in the final submitted report.